Conventionally, as an LSI (Large Scale Integrated circuit) is realizing higher integration and higher speed, the size of a MISFET (hereinbelow, called “MIS transistor”) is being reduced. A reduction in the thickness of a gate insulating film is being demanded in accordance with the miniaturization of the MIS transistor.
In recent years, therefore, to reduce EOT (Equivalent Oxide Thickness) of the gate insulating film without increasing leak current from a gate, a method of using, as the gate insulating film, a high-dielectric-constant insulating film in place of a conventional silicon oxide film and a silicon nitride film is proposed. The “high-dielectric-constant insulating film” is an insulating film made of a dielectric having relative permittivity higher than that of silicon oxide and silicon oxynitride. An example of the dielectric is a metal oxide containing hafnium (Hf).
In the case of using a high-dielectric-constant insulating film as a gate insulating film and using only a conventional polysilicon film as a gate electrode, the threshold voltage of an MIS transistor cannot be sufficiently lowered. There is consequently a proposed technique of using, as a gate insulating film, a high-dielectric-constant insulating film containing metal such as lanthanum (La) or aluminum (Al) for adjusting threshold voltage and using, as a gate electrode, a metal containing film or a stack film of a metal containing film and a silicon film (refer to, for example, PTL 1). In the case of an n-type MIS transistor, by using an Hf-based film containing La as a gate insulating film, the threshold voltage of an n-type MIS transistor can be lowered. On the other hand, in the case of a p-type MIS transistor, by using an Hf-based film containing Al as a gate insulating film, the threshold voltage of a p-type MIS transistor can be lowered.
The configuration of a conventional semiconductor device will be described below with reference to FIGS. 10A to 10C. FIG. 10A is a plan view showing the configuration of the conventional semiconductor device. FIG. 10B is a cross section in the gate width direction showing the configuration of the conventional semiconductor device. FIG. 10C is a cross section in the gate length direction showing the configuration of the conventional semiconductor device. Specifically, FIG. 10B is a cross section taken along ling 10B-10B shown in FIG. 10A. The left side (NTR) in FIG. 10C is a cross section taken along line 10CN-10CN shown in FIG. 10A. The right side (PTR) in FIG. 10C is a cross section taken along line 10CP-10CP shown in FIG. 10A. In FIG. 10A, only an active region, a high-dielectric-constant insulating film in a gate insulating film, and a silicon film in a gate electrode are illustrated and the other components are not shown.
As shown in FIGS. 10A to 10C, the conventional semiconductor device has an n-type MIS transistor and a p-type MIS transistor.
The n-type MIS transistor has p-type well region 103a formed in the n-type transistor region NTR in semiconductor substrate 101, and active region 101a surrounded by device isolation region 102 in semiconductor substrate 101 (p-type well region 103a). The n-type MIS transistor has gate insulating film 106a formed on active region 101a and device isolation region 102 and gate electrode 109a formed on gate insulating film 106a. The n-type MIS transistor has n-type extension regions 110a formed below the sides of gate electrode 109a in active region 101a and sidewalls 111a formed on the side faces of gate electrode 109a. The n-type MIS transistor has n-type source drain regions 112a formed below the outer sides of the sidewalls 111a in active region 101a. 
Gate insulating film 106a has silicon oxide film 104a and high-dielectric-constant insulating film 105a containing La. Gate electrode 109a has titanium nitride film (TiN film) 107a and polysilicon film 108a. 
The p-type MIS transistor has n-type well region 103b formed in the p-type transistor region PTR in semiconductor substrate 101, and active region 101b surrounded by device isolation region 102 in semiconductor substrate 101 (n-type well region 103b). The p-type MIS transistor has gate insulating film 106b formed on active region 101b and device isolation region 102 and gate electrode 109b formed on gate insulating film 106b. The p-type MIS transistor has p-type extension regions 110b formed below the sides of gate electrode 109b in active region 101b and sidewalls 111b formed on the side faces of gate electrode 109b. The p-type MIS transistor has p-type source drain regions 112b formed below the outer sides of sidewalls 111b in active region 101b. 
Gate insulating film 106b has silicon oxide film 104b and high-dielectric-constant insulating film 105b containing Al. Gate electrode 109b has TiN film 107b and polysilicon film 108b. 
The n-type MIS transistor and the p-type MIS transistor construct a CMIS (Complementary Metal Insulator Semiconductor) transistor having dual gate electrodes. Active regions 101a and 101b are isolated from each other while sandwiching the device isolation part therebetween. Gate electrodes 109a and 109b are connected to each other and integrally formed above the device isolation part. The “device isolation part” is a part positioned between active regions 101a and 101b in device isolation region 102.
As shown in FIG. 10B, one side face 105ax in the gate width direction of high-dielectric-constant insulating film 105a matches the side face in the gate width direction of gate electrode 109a. Other side face 105ay in the gate width direction of high-dielectric-constant insulating film 105a is positioned above the center of the device isolation part.